The present invention relates to a logic circuit of TTL (transistor-transistor logic), and particularly to a logic circuit that is adapted to a large-scale PLA (programmable logic array) which consumes reduced amount of electric power owing to the division of the array into circuit blocks.
In dealing with the PLA based upon TTL, if the number of input lines is doubled from n to 2n, the consumption of electric power abnormally increases by 2.sup.n times Therefore, a standard design technique has been to divide the PLA circuit into a plurality of blocks to operate required blocks only, in order to reduce the consumption of electric power. FIG. 1 shows a fundamental logic circuit which constitutes such a block.
In FIG. 1 where inputs I1 to I5 are all assuming a high potential level, if now the input I1 only changes to ground level, an electric current of a current source IM flowing into the base of a multi-emitter npn transistor QM1 is allowed to flow into the input I1 via a first emitter of the transistor QM1. Therefore, the transistor QM1 goes into a conductive state, and the collector potential quickly changes a level close to ground voltage due to the amplification of current. Therefore, npn transistors QN1, QN2 are instantaneously rendered nonconductive and, then, pnp transistors QP1, QP2 are rendered nonconductive, so that no current flows into the base of the multi-emitter npn transistor QM2 and the npn transistor QN3 is rendered nonconductive.
In the above-mentioned operation, no power is consumed by the transistor QM2 as long as the transistor QP2 remains nonconductive. That is, a low-power type PLA is realized in which the electric power is not consumed by unnecessary portions. In this connection, logic circuits have also been disclosed in Japanese patent publication No. 33729/1983 and Japanese patent Laid-Open No. 120386/1978.
In carrying out the above-mentioned operation, however, when the transistor QP2 is rendered nonconductive so that no current flows into the base of the transistor QM2 and that the transistor QN3 is rendered nonconductive, a time is required to extinguish minority carriers that are stored in the collector of the transistor QM2 and in the base and emitter of the transistor QN3. Therefore, the timing for rendering the transistor QN3 nonconductive is delayed, making it difficult to perform the operation at high speeds.